1. Field of the Invention
The present invention relates to an electronic component embedded substrate.
2. Description of the Related Art
As the recently released mobile devices such as smartphones and tablet PCs have been dramatically improved in performance and demanded to have high portability, studies on miniaturization, slimming, and high performance of electronic components used in these mobile devices have been continuously made.
Here, since an electronic component embedded substrate disclosed in Patent Document 1 etc. can secure a space for mounting extra components on its surface by embedding electronic components in a substrate, it has been highlighted as a way of implementing the miniaturization, slimming, and high performance of the electronic components mounted in the mobile devices.
In particular, as the performance of semiconductor chips is improved, stability of power supplied to the semiconductor chips is considered as important. For this, a decoupling capacitor or a bypass capacitor is provided between the semiconductor chip and a power supply line to remove noise of power and supply a stable current to the semiconductor chip in a situation in which a power supply current is being changed suddenly.
At this time, when mounting the semiconductor chip on the capacitor embedded substrate, since a distance between the decoupling capacitor and the semiconductor chip is minimized, it is possible to implement miniaturization and slimming while stably supplying power to the high performance semiconductor chip.
Meanwhile, according to Patent Document 1, a method of fixing a capacitor after processing a cavity in a position where an electronic component is to be inserted, embedding the electronic component by thermocompression using an insulator, processing a micro via hole with laser, and achieving electrical connection through plating is disclosed.
That is, in order to electrically connect between the electronic component embedded in a substrate and a circuit pattern provided on a surface of the substrate, a method of processing a via hole using laser and filling a conductive material in the via hole by a method such as plating has been commonly applied.
According to this common method, minimum conditions on the area of a via contact which is to be formed in the embedded electronic component can be determined according to factors such as placing tolerance generated when the electronic component is embedded in the substrate, via hole processing tolerance, and via hole size.
However, since the size of the via contact should be reduced according to a reduction in the size of the electronic component, as the electronic component becomes smaller, a matching error of the via and the electronic component is emerged as a serious problem.